module	BKP_TRANSCEIVER_4(
   input                         GTM_BKP_RESET,
   input                         TRSV_IN_RFCLK_P,
   input                         TRSV_IN_RFCLK_N,
   input                         TRSV_IN_STARTUP_CLOCK,           // clock used to Transceiver initial and calibration, 10MHz-50MHz

   input                         TRSV_AFE_0_RXDATA_P,
   input                         TRSV_AFE_0_RXDATA_N,
   output                        TRSV_AFE_0_TXDATA_P,
   output                        TRSV_AFE_0_TXDATA_N,
   output                        TRSV_0_OUT_RXCLK,
   output[15:0]                  TRSV_0_OUT_RXDATA,
   output                        TRSV_0_OUT_TXCLK,
   input[15:0]                   TRSV_0_IN_TXDATA,

   input                         TRSV_AFE_1_RXDATA_P,
   input                         TRSV_AFE_1_RXDATA_N,
   output                        TRSV_AFE_1_TXDATA_P,
   output                        TRSV_AFE_1_TXDATA_N,
   output                        TRSV_1_OUT_RXCLK,
   output[15:0]                  TRSV_1_OUT_RXDATA,
   output                        TRSV_1_OUT_TXCLK,
   input[15:0]                   TRSV_1_IN_TXDATA,

   input                         TRSV_AFE_2_RXDATA_P,
   input                         TRSV_AFE_2_RXDATA_N,
   output                        TRSV_AFE_2_TXDATA_P,
   output                        TRSV_AFE_2_TXDATA_N,
   output                        TRSV_2_OUT_RXCLK,
   output[15:0]                  TRSV_2_OUT_RXDATA,
   output                        TRSV_2_OUT_TXCLK,
   input[15:0]                   TRSV_2_IN_TXDATA,

   input                         TRSV_AFE_3_RXDATA_P,
   input                         TRSV_AFE_3_RXDATA_N,
   output                        TRSV_AFE_3_TXDATA_P,
   output                        TRSV_AFE_3_TXDATA_N,
   output                        TRSV_3_OUT_RXCLK,
   output[15:0]                  TRSV_3_OUT_RXDATA,
   output                        TRSV_3_OUT_TXCLK,
   input[15:0]                   TRSV_3_IN_TXDATA,


   // QPLL control
   input                         MPI_IN_QPLLRESET,
   output                        MPI_OUT_QPLLLOCK,
   output                        MPI_OUT_QPLLREFCLKLOST,
   // loopback control
   input[2:0]                    MPI_IN_TRSV_0_LOOPBACK,
   input[2:0]                    MPI_IN_TRSV_1_LOOPBACK,
   input[2:0]                    MPI_IN_TRSV_2_LOOPBACK,
   input[2:0]                    MPI_IN_TRSV_3_LOOPBACK,

   input[3:0]                    MPI_IN_RESET,
   output[3:0]                   MPI_IN_RX_RESET_DONE,
   output[3:0]                   MPI_IN_TX_RESET_DONE,

   output[3:0]                   MPI_OUT_EYESCANERR,
   output[3:0]                   MPI_OUT_RXCDRLOCK
   );


wire[2:0]                     GTX_0_LOOPBACK, GTX_1_LOOPBACK, GTX_2_LOOPBACK, GTX_3_LOOPBACK, GTX_4_LOOPBACK, GTX_5_LOOPBACK, GTX_6_LOOPBACK, GTX_7_LOOPBACK;
wire                          GTX_0_RXUSERRDY, GTX_1_RXUSERRDY, GTX_2_RXUSERRDY, GTX_3_RXUSERRDY, GTX_4_RXUSERRDY, GTX_5_RXUSERRDY, GTX_6_RXUSERRDY, GTX_7_RXUSERRDY;
wire                          GTX_0_EYESCANDATAERROR, GTX_1_EYESCANDATAERROR, GTX_2_EYESCANDATAERROR, GTX_3_EYESCANDATAERROR, GTX_4_EYESCANDATAERROR, GTX_5_EYESCANDATAERROR, GTX_6_EYESCANDATAERROR, GTX_7_EYESCANDATAERROR;
wire                          GTX_0_RXCDRLOCK, GTX_1_RXCDRLOCK, GTX_2_RXCDRLOCK, GTX_3_RXCDRLOCK, GTX_4_RXCDRLOCK, GTX_5_RXCDRLOCK, GTX_6_RXCDRLOCK, GTX_7_RXCDRLOCK;
wire                          GTX_0_RXUSRCLK, GTX_1_RXUSRCLK, GTX_2_RXUSRCLK, GTX_3_RXUSRCLK, GTX_4_RXUSRCLK, GTX_5_RXUSRCLK, GTX_6_RXUSRCLK, GTX_7_RXUSRCLK;
wire                          GTX_0_RXUSRCLK2, GTX_1_RXUSRCLK2, GTX_2_RXUSRCLK2, GTX_3_RXUSRCLK2, GTX_4_RXUSRCLK2, GTX_5_RXUSRCLK2, GTX_6_RXUSRCLK2, GTX_7_RXUSRCLK2;
wire[15:0]                    GTX_0_RXDATA, GTX_1_RXDATA, GTX_2_RXDATA, GTX_3_RXDATA, GTX_4_RXDATA, GTX_5_RXDATA, GTX_6_RXDATA, GTX_7_RXDATA;
wire                          GTX_0_GTXRXP, GTX_1_GTXRXP, GTX_2_GTXRXP, GTX_3_GTXRXP, GTX_4_GTXRXP, GTX_5_GTXRXP, GTX_6_GTXRXP, GTX_7_GTXRXP;
wire                          GTX_0_GTXRXN, GTX_1_GTXRXN, GTX_2_GTXRXN, GTX_3_GTXRXN, GTX_4_GTXRXN, GTX_5_GTXRXN, GTX_6_GTXRXN, GTX_7_GTXRXN;
wire                          GTX_0_RXDFEAGCHOLD, GTX_1_RXDFEAGCHOLD, GTX_2_RXDFEAGCHOLD, GTX_3_RXDFEAGCHOLD, GTX_4_RXDFEAGCHOLD, GTX_5_RXDFEAGCHOLD, GTX_6_RXDFEAGCHOLD, GTX_7_RXDFEAGCHOLD;
wire                          GTX_0_RXOUTCLK, GTX_1_RXOUTCLK, GTX_2_RXOUTCLK, GTX_3_RXOUTCLK, GTX_4_RXOUTCLK, GTX_5_RXOUTCLK, GTX_6_RXOUTCLK, GTX_7_RXOUTCLK;
wire                          GTX_0_GTRXRESET, GTX_1_GTRXRESET, GTX_2_GTRXRESET, GTX_3_GTRXRESET, GTX_4_GTRXRESET, GTX_5_GTRXRESET, GTX_6_GTRXRESET, GTX_7_GTRXRESET;
wire                          GTX_0_RXPCSRESET, GTX_1_RXPCSRESET, GTX_2_RXPCSRESET, GTX_3_RXPCSRESET, GTX_4_RXPCSRESET, GTX_5_RXPCSRESET, GTX_6_RXPCSRESET, GTX_7_RXPCSRESET;
wire                          GTX_0_RXPMARESET, GTX_1_RXPMARESET, GTX_2_RXPMARESET, GTX_3_RXPMARESET, GTX_4_RXPMARESET, GTX_5_RXPMARESET, GTX_6_RXPMARESET, GTX_7_RXPMARESET;
wire                          GTX_0_RXRESETDONE, GTX_1_RXRESETDONE, GTX_2_RXRESETDONE, GTX_3_RXRESETDONE, GTX_4_RXRESETDONE, GTX_5_RXRESETDONE, GTX_6_RXRESETDONE, GTX_7_RXRESETDONE;
wire                          GTX_0_GTTXRESET, GTX_1_GTTXRESET, GTX_2_GTTXRESET, GTX_3_GTTXRESET, GTX_4_GTTXRESET, GTX_5_GTTXRESET, GTX_6_GTTXRESET, GTX_7_GTTXRESET;
wire                          GTX_0_TXUSERRDY, GTX_1_TXUSERRDY, GTX_2_TXUSERRDY, GTX_3_TXUSERRDY, GTX_4_TXUSERRDY, GTX_5_TXUSERRDY, GTX_6_TXUSERRDY, GTX_7_TXUSERRDY;
wire                          GTX_0_TXUSRCLK, GTX_1_TXUSRCLK, GTX_2_TXUSRCLK, GTX_3_TXUSRCLK, GTX_4_TXUSRCLK, GTX_5_TXUSRCLK, GTX_6_TXUSRCLK, GTX_7_TXUSRCLK;
wire                          GTX_0_TXUSRCLK2, GTX_1_TXUSRCLK2, GTX_2_TXUSRCLK2, GTX_3_TXUSRCLK2, GTX_4_TXUSRCLK2, GTX_5_TXUSRCLK2, GTX_6_TXUSRCLK2, GTX_7_TXUSRCLK2;
wire[1:0]                     GTX_0_TXBUFSTATUS, GTX_1_TXBUFSTATUS, GTX_2_TXBUFSTATUS, GTX_3_TXBUFSTATUS, GTX_4_TXBUFSTATUS, GTX_5_TXBUFSTATUS, GTX_6_TXBUFSTATUS, GTX_7_TXBUFSTATUS;
wire[15:0]                    GTX_0_TXDATA, GTX_1_TXDATA, GTX_2_TXDATA, GTX_3_TXDATA, GTX_4_TXDATA, GTX_5_TXDATA, GTX_6_TXDATA, GTX_7_TXDATA;
wire                          GTX_0_GTXTXN, GTX_1_GTXTXN, GTX_2_GTXTXN, GTX_3_GTXTXN, GTX_4_GTXTXN, GTX_5_GTXTXN, GTX_6_GTXTXN, GTX_7_GTXTXN;
wire                          GTX_0_GTXTXP, GTX_1_GTXTXP, GTX_2_GTXTXP, GTX_3_GTXTXP, GTX_4_GTXTXP, GTX_5_GTXTXP, GTX_6_GTXTXP, GTX_7_GTXTXP;
wire                          GTX_0_TXOUTCLK, GTX_1_TXOUTCLK, GTX_2_TXOUTCLK, GTX_3_TXOUTCLK, GTX_4_TXOUTCLK, GTX_5_TXOUTCLK, GTX_6_TXOUTCLK, GTX_7_TXOUTCLK;
wire                          GTX_0_TXPCSRESET, GTX_1_TXPCSRESET, GTX_2_TXPCSRESET, GTX_3_TXPCSRESET, GTX_4_TXPCSRESET, GTX_5_TXPCSRESET, GTX_6_TXPCSRESET, GTX_7_TXPCSRESET;
wire                          GTX_0_TXRESETDONE, GTX_1_TXRESETDONE, GTX_2_TXRESETDONE, GTX_3_TXRESETDONE, GTX_4_TXRESETDONE, GTX_5_TXRESETDONE, GTX_6_TXRESETDONE, GTX_7_TXRESETDONE;

wire                          GTX_REFCLK, GTX_Q1_REFCLK;
wire                          GTX_QPLLLOCK, GTX_Q1_QPLLLOCK;
wire                          GTX_QPLLLOCKDETCLK, GTX_Q1_QPLLLOCKDETCLK;
wire                          GTX_QPLLREFCLKLOST, GTX_Q1_QPLLREFCLKLOST;
wire                          GTX_QPLLRESET, GTX_Q1_QPLLRESET;

wire[8:0]                     GTX_DRPADDR;
wire                          GTX_DRPCLK;
wire[15:0]                    GTX_DRPDI;
wire                          GTX_DRPEN;
wire                          GTX_DRPWE;


reg[15:0]                     GTX_RESET_CNT;
reg                           GTX_AUTO_RESET;

IBUFDS_GTE2                        IBUFDS_Q0_GTREFCLK(
   .O                              ( GTX_REFCLK ),
   .ODIV2                          (  ),
   .CEB                            ( 1'b0 ),
   .I                              ( TRSV_IN_RFCLK_P ),
   .IB                             ( TRSV_IN_RFCLK_N )
    );

always @( posedge TRSV_IN_STARTUP_CLOCK ) begin
   if ( GTX_QPLLLOCK==1'b0 )
      GTX_RESET_CNT[15:0]                   <= 16'd0;
   else if ( GTX_RESET_CNT[15:0]!=16'hffff )
      GTX_RESET_CNT[15:0]                   <= GTX_RESET_CNT[15:0] +16'd1;
end
always @( posedge TRSV_IN_STARTUP_CLOCK ) begin
   GTX_AUTO_RESET                           <= GTX_RESET_CNT[15:0]!=16'hffff;
end




// GTX channel 0 signals
  assign GTX_0_LOOPBACK[2:0]     = MPI_IN_TRSV_0_LOOPBACK[2:0];
  assign GTX_0_GTRXRESET         = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_0_RXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_0_RXPMARESET        = 1'b0;
  assign GTX_0_RXDFEAGCHOLD      = 1'b0;

  assign MPI_OUT_EYESCANERR[0]   = GTX_0_EYESCANDATAERROR;
  assign MPI_OUT_RXCDRLOCK[0]    = GTX_0_RXCDRLOCK;
  assign MPI_IN_RX_RESET_DONE[0] = GTX_0_RXRESETDONE;

  assign TRSV_0_OUT_RXDATA[15:0] = GTX_0_RXDATA[15:0];
  assign TRSV_0_OUT_RXCLK        = GTX_0_RXUSRCLK;
  assign GTX_0_GTXRXN            = TRSV_AFE_0_RXDATA_N;
  assign GTX_0_GTXRXP            = TRSV_AFE_0_RXDATA_P;
  assign GTX_0_RXUSERRDY         = 1'b1;
  assign GTX_0_RXUSRCLK2         = GTX_0_RXUSRCLK;
  BUFG  GTX_0_RX_BUFG( .O( GTX_0_RXUSRCLK ),       .I( GTX_0_RXOUTCLK ));
   

  assign GTX_0_GTTXRESET         = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_0_TXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign MPI_IN_TX_RESET_DONE[0] = GTX_0_TXRESETDONE;

  assign TRSV_AFE_0_TXDATA_N     = GTX_0_GTXTXN;
  assign TRSV_AFE_0_TXDATA_P     = GTX_0_GTXTXP;
  assign GTX_0_TXUSERRDY         = 1'b1;
  assign GTX_0_TXDATA[15:0]      = TRSV_0_IN_TXDATA[15:0];
  assign TRSV_0_OUT_TXCLK        = GTX_0_TXUSRCLK;
  assign GTX_0_TXUSRCLK2         = GTX_0_TXUSRCLK;
  BUFH  GTX_0_TX_BUFH( .O( GTX_0_TXUSRCLK ),       .I( GTX_0_TXOUTCLK ));



// GTX channel 1 signals
  assign GTX_1_LOOPBACK[2:0]     = MPI_IN_TRSV_1_LOOPBACK[2:0];
  assign GTX_1_GTRXRESET         = MPI_IN_RESET[1] | GTX_AUTO_RESET;
  assign GTX_1_RXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_1_RXPMARESET        = 1'b0;
  assign GTX_1_RXDFEAGCHOLD      = 1'b0;

  assign MPI_OUT_EYESCANERR[1]   = GTX_1_EYESCANDATAERROR;
  assign MPI_OUT_RXCDRLOCK[1]    = GTX_1_RXCDRLOCK;
  assign MPI_IN_RX_RESET_DONE[1] =GTX_1_RXRESETDONE;

  assign TRSV_1_OUT_RXDATA[15:0] = GTX_1_RXDATA[15:0];
  assign TRSV_1_OUT_RXCLK        = GTX_1_RXUSRCLK;
  assign GTX_1_GTXRXN            = TRSV_AFE_1_RXDATA_N;
  assign GTX_1_GTXRXP            = TRSV_AFE_1_RXDATA_P;
  assign GTX_1_RXUSERRDY         = 1'b1;
  assign GTX_1_RXUSRCLK2         = GTX_1_RXUSRCLK;
  BUFG  GTX_1_RX_BUFG( .O( GTX_1_RXUSRCLK ),       .I( GTX_1_RXOUTCLK ));
   

  assign GTX_1_GTTXRESET         = MPI_IN_RESET[1] | GTX_AUTO_RESET;
  assign GTX_1_TXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign MPI_IN_TX_RESET_DONE[1] = GTX_1_TXRESETDONE;

  assign TRSV_AFE_1_TXDATA_N     = GTX_1_GTXTXN;
  assign TRSV_AFE_1_TXDATA_P     = GTX_1_GTXTXP;
  assign GTX_1_TXUSERRDY         = 1'b1;
  assign GTX_1_TXDATA[15:0]      = TRSV_1_IN_TXDATA[15:0];
  assign TRSV_1_OUT_TXCLK        = GTX_1_TXUSRCLK;
  assign GTX_1_TXUSRCLK2         = GTX_1_TXUSRCLK;
  BUFH  GTX_1_TX_BUFH( .O( GTX_1_TXUSRCLK ),       .I( GTX_1_TXOUTCLK ));



// GTX channel 2 signals
  assign GTX_2_LOOPBACK[2:0]     = MPI_IN_TRSV_2_LOOPBACK[2:0];
  assign GTX_2_GTRXRESET         = MPI_IN_RESET[2] | GTX_AUTO_RESET;
  assign GTX_2_RXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_2_RXPMARESET        = 1'b0;
  assign GTX_2_RXDFEAGCHOLD      = 1'b0;

  assign MPI_OUT_EYESCANERR[2]   = GTX_2_EYESCANDATAERROR;
  assign MPI_OUT_RXCDRLOCK[2]    = GTX_2_RXCDRLOCK;
  assign MPI_IN_RX_RESET_DONE[2] =GTX_2_RXRESETDONE;

  assign TRSV_2_OUT_RXDATA[15:0] = GTX_2_RXDATA[15:0];
  assign TRSV_2_OUT_RXCLK        = GTX_2_RXUSRCLK;
  assign GTX_2_GTXRXN            = TRSV_AFE_2_RXDATA_N;
  assign GTX_2_GTXRXP            = TRSV_AFE_2_RXDATA_P;
  assign GTX_2_RXUSERRDY         = 1'b1;
  assign GTX_2_RXUSRCLK2         = GTX_2_RXUSRCLK;
  BUFG  GTX_2_RX_BUFG( .O( GTX_2_RXUSRCLK ),       .I( GTX_2_RXOUTCLK ));
   

  assign GTX_2_GTTXRESET         = MPI_IN_RESET[2] | GTX_AUTO_RESET;
  assign GTX_2_TXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign MPI_IN_TX_RESET_DONE[2] = GTX_2_TXRESETDONE;

  assign TRSV_AFE_2_TXDATA_N     = GTX_2_GTXTXN;
  assign TRSV_AFE_2_TXDATA_P     = GTX_2_GTXTXP;
  assign GTX_2_TXUSERRDY         = 1'b1;
  assign GTX_2_TXDATA[15:0]      = TRSV_2_IN_TXDATA[15:0];
  assign TRSV_2_OUT_TXCLK        = GTX_2_TXUSRCLK;
  assign GTX_2_TXUSRCLK2         = GTX_2_TXUSRCLK;
  BUFH  GTX_2_TX_BUFH( .O( GTX_2_TXUSRCLK ),       .I( GTX_2_TXOUTCLK ));



// GTX channel 3 signals
  assign GTX_3_LOOPBACK[2:0]     = MPI_IN_TRSV_3_LOOPBACK[2:0];
  assign GTX_3_GTRXRESET         = MPI_IN_RESET[3] | GTX_AUTO_RESET;
  assign GTX_3_RXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign GTX_3_RXPMARESET        = 1'b0;
  assign GTX_3_RXDFEAGCHOLD      = 1'b0;

  assign MPI_OUT_EYESCANERR[3]   = GTX_3_EYESCANDATAERROR;
  assign MPI_OUT_RXCDRLOCK[3]    = GTX_3_RXCDRLOCK;
  assign MPI_IN_RX_RESET_DONE[3] =GTX_3_RXRESETDONE;

  assign TRSV_3_OUT_RXDATA[15:0] = GTX_3_RXDATA[15:0];
  assign TRSV_3_OUT_RXCLK        = GTX_3_RXUSRCLK;
  assign GTX_3_GTXRXN            = TRSV_AFE_3_RXDATA_N;
  assign GTX_3_GTXRXP            = TRSV_AFE_3_RXDATA_P;
  assign GTX_3_RXUSERRDY         = 1'b1;
  assign GTX_3_RXUSRCLK2         = GTX_3_RXUSRCLK;
  BUFG  GTX_3_RX_BUFG( .O( GTX_3_RXUSRCLK ),       .I( GTX_3_RXOUTCLK ));
   

  assign GTX_3_GTTXRESET         = MPI_IN_RESET[3] | GTX_AUTO_RESET;
  assign GTX_3_TXPCSRESET        = MPI_IN_RESET[0] | GTX_AUTO_RESET;
  assign MPI_IN_TX_RESET_DONE[3] = GTX_3_TXRESETDONE;

  assign TRSV_AFE_3_TXDATA_N     = GTX_3_GTXTXN;
  assign TRSV_AFE_3_TXDATA_P     = GTX_3_GTXTXP;
  assign GTX_3_TXUSERRDY         = 1'b1;
  assign GTX_3_TXDATA[15:0]      = TRSV_3_IN_TXDATA[15:0];
  assign TRSV_3_OUT_TXCLK        = GTX_3_TXUSRCLK;
  assign GTX_3_TXUSRCLK2         = GTX_3_TXUSRCLK;
  BUFH  GTX_3_TX_BUFH( .O( GTX_3_TXUSRCLK ),       .I( GTX_3_TXOUTCLK ));


  assign MPI_OUT_QPLLLOCK        = GTX_QPLLLOCK;
  assign MPI_OUT_QPLLREFCLKLOST  = GTX_QPLLREFCLKLOST;
  assign GTX_QPLLRESET           = MPI_IN_QPLLRESET ;
  assign GTX_QPLLLOCKDETCLK      = TRSV_IN_STARTUP_CLOCK;

  assign GTX_DRPADDR[8:0]        = 9'd0;
  assign GTX_DRPCLK              = TRSV_IN_STARTUP_CLOCK;
  assign GTX_DRPDI[15:0]         = 16'd0;
  assign GTX_DRPEN               = 1'b0;
  assign GTX_DRPWE               = 1'b0;
  

/*BKP_GTX_8                            INST_BKP_GTX_8(
    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT0  (X0Y0)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT0_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT0_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT0_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT0_DRPDO_OUT                   (  ),
    .GT0_DRPEN_IN                    ( GTX_DRPEN ),
    .GT0_DRPRDY_OUT                  (  ),
    .GT0_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT0_LOOPBACK_IN                 ( GTX_0_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT0_RXUSERRDY_IN                ( GTX_0_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT0_EYESCANDATAERROR_OUT        ( GTX_0_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT0_RXCDRLOCK_OUT               ( GTX_0_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT0_RXUSRCLK_IN                 ( GTX_0_RXUSRCLK ),
    .GT0_RXUSRCLK2_IN                ( GTX_0_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT0_RXDATA_OUT                  ( GTX_0_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT0_GTXRXP_IN                   ( GTX_0_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT0_GTXRXN_IN                   ( GTX_0_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT0_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT0_RXDFEAGCHOLD_IN             ( GTX_0_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT0_RXOUTCLK_OUT                ( GTX_0_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT0_GTRXRESET_IN                ( GTX_0_GTRXRESET ),
    .GT0_RXPCSRESET_IN               ( GTX_0_RXPCSRESET ),
    .GT0_RXPMARESET_IN               ( GTX_0_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT0_RXRESETDONE_OUT             ( GTX_0_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT0_GTTXRESET_IN                ( GTX_0_GTTXRESET ),
    .GT0_TXUSERRDY_IN                ( GTX_0_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT0_TXUSRCLK_IN                 ( GTX_0_TXUSRCLK ),
    .GT0_TXUSRCLK2_IN                ( GTX_0_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT0_TXBUFSTATUS_OUT             ( GTX_0_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT0_TXDATA_IN                   ( GTX_0_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT0_GTXTXN_OUT                  ( GTX_0_GTXTXN ),
    .GT0_GTXTXP_OUT                  ( GTX_0_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT0_TXOUTCLK_OUT                ( GTX_0_TXOUTCLK ),
    .GT0_TXOUTCLKFABRIC_OUT          (  ),
    .GT0_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT0_TXPCSRESET_IN               ( GTX_0_TXPCSRESET ),
    .GT0_TXRESETDONE_OUT             ( GTX_0_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT1  (X0Y1)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT1_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT1_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT1_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT1_DRPDO_OUT                   (  ),
    .GT1_DRPEN_IN                    ( GTX_DRPEN ),
    .GT1_DRPRDY_OUT                  (  ),
    .GT1_DRPWE_IN                    ( GTX_DRPWE ),

    //----------------------------- Loopback Ports -----------------------------
    .GT1_LOOPBACK_IN                 ( GTX_1_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT1_RXUSERRDY_IN                ( GTX_1_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT1_EYESCANDATAERROR_OUT        ( GTX_1_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT1_RXCDRLOCK_OUT               ( GTX_1_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT1_RXUSRCLK_IN                 ( GTX_1_RXUSRCLK ),
    .GT1_RXUSRCLK2_IN                ( GTX_1_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT1_RXDATA_OUT                  ( GTX_1_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT1_GTXRXP_IN                   ( GTX_1_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT1_GTXRXN_IN                   ( GTX_1_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT1_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT1_RXDFEAGCHOLD_IN             ( GTX_1_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT1_RXOUTCLK_OUT                ( GTX_1_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT1_GTRXRESET_IN                ( GTX_1_GTRXRESET ),
    .GT1_RXPCSRESET_IN               ( GTX_1_RXPCSRESET ),
    .GT1_RXPMARESET_IN               ( GTX_1_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT1_RXRESETDONE_OUT             ( GTX_1_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT1_GTTXRESET_IN                ( GTX_1_GTTXRESET ),
    .GT1_TXUSERRDY_IN                ( GTX_1_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT1_TXUSRCLK_IN                 ( GTX_1_TXUSRCLK ),
    .GT1_TXUSRCLK2_IN                ( GTX_1_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT1_TXBUFSTATUS_OUT             ( GTX_1_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT1_TXDATA_IN                   ( GTX_1_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT1_GTXTXN_OUT                  ( GTX_1_GTXTXN ),
    .GT1_GTXTXP_OUT                  ( GTX_1_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT1_TXOUTCLK_OUT                ( GTX_1_TXOUTCLK ),
    .GT1_TXOUTCLKFABRIC_OUT          (  ),
    .GT1_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT1_TXPCSRESET_IN               ( GTX_1_TXPCSRESET ),
    .GT1_TXRESETDONE_OUT             ( GTX_1_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT2  (X0Y2)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT2_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT2_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT2_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT2_DRPDO_OUT                   (  ),
    .GT2_DRPEN_IN                    ( GTX_DRPEN ),
    .GT2_DRPRDY_OUT                  (  ),
    .GT2_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT2_LOOPBACK_IN                 ( GTX_2_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT2_RXUSERRDY_IN                ( GTX_2_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT2_EYESCANDATAERROR_OUT        ( GTX_2_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT2_RXCDRLOCK_OUT               ( GTX_2_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT2_RXUSRCLK_IN                 ( GTX_2_RXUSRCLK ),
    .GT2_RXUSRCLK2_IN                ( GTX_2_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT2_RXDATA_OUT                  ( GTX_2_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT2_GTXRXP_IN                   ( GTX_2_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT2_GTXRXN_IN                   ( GTX_2_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT2_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT2_RXDFEAGCHOLD_IN             ( GTX_2_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT2_RXOUTCLK_OUT                ( GTX_2_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT2_GTRXRESET_IN                ( GTX_2_GTRXRESET ),
    .GT2_RXPCSRESET_IN               ( GTX_2_RXPCSRESET ),
    .GT2_RXPMARESET_IN               ( GTX_2_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT2_RXRESETDONE_OUT             ( GTX_2_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT2_GTTXRESET_IN                ( GTX_2_GTTXRESET ),
    .GT2_TXUSERRDY_IN                ( GTX_2_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT2_TXUSRCLK_IN                 ( GTX_2_TXUSRCLK ),
    .GT2_TXUSRCLK2_IN                ( GTX_2_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT2_TXBUFSTATUS_OUT             ( GTX_2_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT2_TXDATA_IN                   ( GTX_2_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT2_GTXTXN_OUT                  ( GTX_2_GTXTXN ),
    .GT2_GTXTXP_OUT                  ( GTX_2_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT2_TXOUTCLK_OUT                ( GTX_2_TXOUTCLK ),
    .GT2_TXOUTCLKFABRIC_OUT          (  ),
    .GT2_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT2_TXPCSRESET_IN               ( GTX_2_TXPCSRESET ),
    .GT2_TXRESETDONE_OUT             ( GTX_2_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT3  (X0Y3)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT3_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT3_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT3_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT3_DRPDO_OUT                   (  ),
    .GT3_DRPEN_IN                    ( GTX_DRPEN ),
    .GT3_DRPRDY_OUT                  (  ),
    .GT3_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT3_LOOPBACK_IN                 ( GTX_3_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT3_RXUSERRDY_IN                ( GTX_3_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT3_EYESCANDATAERROR_OUT        ( GTX_3_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT3_RXCDRLOCK_OUT               ( GTX_3_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT3_RXUSRCLK_IN                 ( GTX_3_RXUSRCLK ),
    .GT3_RXUSRCLK2_IN                ( GTX_3_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT3_RXDATA_OUT                  ( GTX_3_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT3_GTXRXP_IN                   ( GTX_3_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT3_GTXRXN_IN                   ( GTX_3_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT3_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT3_RXDFEAGCHOLD_IN             ( GTX_3_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT3_RXOUTCLK_OUT                ( GTX_3_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT3_GTRXRESET_IN                ( GTX_3_GTRXRESET ),
    .GT3_RXPCSRESET_IN               ( GTX_3_RXPCSRESET ),
    .GT3_RXPMARESET_IN               ( GTX_3_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT3_RXRESETDONE_OUT             ( GTX_3_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT3_GTTXRESET_IN                ( GTX_3_GTTXRESET ),
    .GT3_TXUSERRDY_IN                ( GTX_3_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT3_TXUSRCLK_IN                 ( GTX_3_TXUSRCLK ),
    .GT3_TXUSRCLK2_IN                ( GTX_3_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT3_TXBUFSTATUS_OUT             ( GTX_3_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT3_TXDATA_IN                   ( GTX_3_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT3_GTXTXN_OUT                  ( GTX_3_GTXTXN ),
    .GT3_GTXTXP_OUT                  ( GTX_3_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT3_TXOUTCLK_OUT                ( GTX_3_TXOUTCLK ),
    .GT3_TXOUTCLKFABRIC_OUT          (  ),
    .GT3_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT3_TXPCSRESET_IN               ( GTX_3_TXPCSRESET ),
    .GT3_TXRESETDONE_OUT             ( GTX_3_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT4  (X0Y4)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT4_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT4_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT4_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT4_DRPDO_OUT                   (  ),
    .GT4_DRPEN_IN                    ( GTX_DRPEN ),
    .GT4_DRPRDY_OUT                  (  ),
    .GT4_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT4_LOOPBACK_IN                 ( GTX_4_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT4_RXUSERRDY_IN                ( GTX_4_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT4_EYESCANDATAERROR_OUT        ( GTX_4_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT4_RXCDRLOCK_OUT               ( GTX_4_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT4_RXUSRCLK_IN                 ( GTX_4_RXUSRCLK ),
    .GT4_RXUSRCLK2_IN                ( GTX_4_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT4_RXDATA_OUT                  ( GTX_4_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT4_GTXRXP_IN                   ( GTX_4_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT4_GTXRXN_IN                   ( GTX_4_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT4_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT4_RXDFEAGCHOLD_IN             ( GTX_4_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT4_RXOUTCLK_OUT                ( GTX_4_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT4_GTRXRESET_IN                ( GTX_4_GTRXRESET ),
    .GT4_RXPCSRESET_IN               ( GTX_4_RXPCSRESET ),
    .GT4_RXPMARESET_IN               ( GTX_4_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT4_RXRESETDONE_OUT             ( GTX_4_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT4_GTTXRESET_IN                ( GTX_4_GTTXRESET ),
    .GT4_TXUSERRDY_IN                ( GTX_4_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT4_TXUSRCLK_IN                 ( GTX_4_TXUSRCLK ),
    .GT4_TXUSRCLK2_IN                ( GTX_4_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT4_TXBUFSTATUS_OUT             ( GTX_4_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT4_TXDATA_IN                   ( GTX_4_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT4_GTXTXN_OUT                  ( GTX_4_GTXTXN ),
    .GT4_GTXTXP_OUT                  ( GTX_4_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT4_TXOUTCLK_OUT                ( GTX_4_TXOUTCLK ),
    .GT4_TXOUTCLKFABRIC_OUT          (  ),
    .GT4_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT4_TXPCSRESET_IN               ( GTX_4_TXPCSRESET ),
    .GT4_TXRESETDONE_OUT             ( GTX_4_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT5  (X0Y5)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT5_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT5_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT5_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT5_DRPDO_OUT                   (  ),
    .GT5_DRPEN_IN                    ( GTX_DRPEN ),
    .GT5_DRPRDY_OUT                  (  ),
    .GT5_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT5_LOOPBACK_IN                 ( GTX_5_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT5_RXUSERRDY_IN                ( GTX_5_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT5_EYESCANDATAERROR_OUT        ( GTX_5_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT5_RXCDRLOCK_OUT               ( GTX_5_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT5_RXUSRCLK_IN                 ( GTX_5_RXUSRCLK ),
    .GT5_RXUSRCLK2_IN                ( GTX_5_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT5_RXDATA_OUT                  ( GTX_5_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT5_GTXRXP_IN                   ( GTX_5_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT5_GTXRXN_IN                   ( GTX_5_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT5_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT5_RXDFEAGCHOLD_IN             ( GTX_5_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT5_RXOUTCLK_OUT                ( GTX_5_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT5_GTRXRESET_IN                ( GTX_5_GTRXRESET ),
    .GT5_RXPCSRESET_IN               ( GTX_5_RXPCSRESET ),
    .GT5_RXPMARESET_IN               ( GTX_5_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT5_RXRESETDONE_OUT             ( GTX_5_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT5_GTTXRESET_IN                ( GTX_5_GTTXRESET ),
    .GT5_TXUSERRDY_IN                ( GTX_5_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT5_TXUSRCLK_IN                 ( GTX_5_TXUSRCLK ),
    .GT5_TXUSRCLK2_IN                ( GTX_5_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT5_TXBUFSTATUS_OUT             ( GTX_5_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT5_TXDATA_IN                   ( GTX_5_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT5_GTXTXN_OUT                  ( GTX_5_GTXTXN ),
    .GT5_GTXTXP_OUT                  ( GTX_5_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT5_TXOUTCLK_OUT                ( GTX_5_TXOUTCLK ),
    .GT5_TXOUTCLKFABRIC_OUT          (  ),
    .GT5_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT5_TXPCSRESET_IN               ( GTX_5_TXPCSRESET ),
    .GT5_TXRESETDONE_OUT             ( GTX_5_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT6  (X0Y6)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT6_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT6_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT6_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT6_DRPDO_OUT                   (  ),
    .GT6_DRPEN_IN                    ( GTX_DRPEN ),
    .GT6_DRPRDY_OUT                  (  ),
    .GT6_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT6_LOOPBACK_IN                 ( GTX_6_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT6_RXUSERRDY_IN                ( GTX_6_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT6_EYESCANDATAERROR_OUT        ( GTX_6_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT6_RXCDRLOCK_OUT               ( GTX_6_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT6_RXUSRCLK_IN                 ( GTX_6_RXUSRCLK ),
    .GT6_RXUSRCLK2_IN                ( GTX_6_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT6_RXDATA_OUT                  ( GTX_6_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT6_GTXRXP_IN                   ( GTX_6_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT6_GTXRXN_IN                   ( GTX_6_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT6_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT6_RXDFEAGCHOLD_IN             ( GTX_6_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT6_RXOUTCLK_OUT                ( GTX_6_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT6_GTRXRESET_IN                ( GTX_6_GTRXRESET ),
    .GT6_RXPCSRESET_IN               ( GTX_6_RXPCSRESET ),
    .GT6_RXPMARESET_IN               ( GTX_6_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT6_RXRESETDONE_OUT             ( GTX_6_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT6_GTTXRESET_IN                ( GTX_6_GTTXRESET ),
    .GT6_TXUSERRDY_IN                ( GTX_6_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT6_TXUSRCLK_IN                 ( GTX_6_TXUSRCLK ),
    .GT6_TXUSRCLK2_IN                ( GTX_6_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT6_TXBUFSTATUS_OUT             ( GTX_6_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT6_TXDATA_IN                   ( GTX_6_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT6_GTXTXN_OUT                  ( GTX_6_GTXTXN ),
    .GT6_GTXTXP_OUT                  ( GTX_6_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT6_TXOUTCLK_OUT                ( GTX_6_TXOUTCLK ),
    .GT6_TXOUTCLKFABRIC_OUT          (  ),
    .GT6_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT6_TXPCSRESET_IN               ( GTX_6_TXPCSRESET ) ,
    .GT6_TXRESETDONE_OUT             ( GTX_6_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT7  (X0Y7)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT7_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT7_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT7_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT7_DRPDO_OUT                   (  ),
    .GT7_DRPEN_IN                    ( GTX_DRPEN ),
    .GT7_DRPRDY_OUT                  (  ),
    .GT7_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT7_LOOPBACK_IN                 ( GTX_7_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT7_RXUSERRDY_IN                ( GTX_7_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT7_EYESCANDATAERROR_OUT        ( GTX_7_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT7_RXCDRLOCK_OUT               ( GTX_7_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT7_RXUSRCLK_IN                 ( GTX_7_RXUSRCLK ),
    .GT7_RXUSRCLK2_IN                ( GTX_7_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT7_RXDATA_OUT                  ( GTX_7_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT7_GTXRXP_IN                   ( GTX_7_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT7_GTXRXN_IN                   ( GTX_7_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT7_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
    .GT7_RXDFEAGCHOLD_IN             ( GTX_7_RXDFEAGCHOLD ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT7_RXOUTCLK_OUT                ( GTX_7_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT7_GTRXRESET_IN                ( GTX_7_GTRXRESET ),
    .GT7_RXPCSRESET_IN               ( GTX_7_RXPCSRESET ),
    .GT7_RXPMARESET_IN               ( GTX_7_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT7_RXRESETDONE_OUT             ( GTX_7_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT7_GTTXRESET_IN                ( GTX_7_GTTXRESET ),
    .GT7_TXUSERRDY_IN                ( GTX_7_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT7_TXUSRCLK_IN                 ( GTX_7_TXUSRCLK ),
    .GT7_TXUSRCLK2_IN                ( GTX_7_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT7_TXBUFSTATUS_OUT             ( GTX_7_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT7_TXDATA_IN                   ( GTX_7_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT7_GTXTXN_OUT                  ( GTX_7_GTXTXN ),
    .GT7_GTXTXP_OUT                  ( GTX_7_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT7_TXOUTCLK_OUT                ( GTX_7_TXOUTCLK ),
    .GT7_TXOUTCLKFABRIC_OUT          (  ),
    .GT7_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT7_TXPCSRESET_IN               ( GTX_7_TXPCSRESET ),
    .GT7_TXRESETDONE_OUT             ( GTX_7_TXRESETDONE ),


    //____________________________COMMON PORTS________________________________
    //-------------------- Common Block  - Ref Clock Ports ---------------------
    .GT0_GTREFCLK0_COMMON_IN         ( GTX_REFCLK ),
    //----------------------- Common Block - QPLL Ports ------------------------
    .GT0_QPLLLOCK_OUT                ( GTX_QPLLLOCK ),
    .GT0_QPLLLOCKDETCLK_IN           ( GTX_QPLLLOCKDETCLK ),
    .GT0_QPLLREFCLKLOST_OUT          ( GTX_QPLLREFCLKLOST ),
    .GT0_QPLLRESET_IN                ( GTX_QPLLRESET ),

    //____________________________COMMON PORTS________________________________
    //-------------------- Common Block  - Ref Clock Ports ---------------------
    .GT1_GTREFCLK0_COMMON_IN         ( GTX_Q1_REFCLK ),
    //----------------------- Common Block - QPLL Ports ------------------------
    .GT1_QPLLLOCK_OUT                ( GTX_Q1_QPLLLOCK ),
    .GT1_QPLLLOCKDETCLK_IN           ( GTX_Q1_QPLLLOCKDETCLK ),
    .GT1_QPLLREFCLKLOST_OUT          ( GTX_Q1_QPLLREFCLKLOST ),
    .GT1_QPLLRESET_IN                ( GTX_Q1_QPLLRESET )


);*/









BKP_GTX_4                            INST_BKP_GTX_4(
    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT0  (X0Y0)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT0_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT0_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT0_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT0_DRPDO_OUT                   (  ),
    .GT0_DRPEN_IN                    ( GTX_DRPEN ),
    .GT0_DRPRDY_OUT                  (  ),
    .GT0_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT0_LOOPBACK_IN                 ( GTX_0_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT0_RXUSERRDY_IN                ( GTX_0_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT0_EYESCANDATAERROR_OUT        ( GTX_0_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT0_RXCDRLOCK_OUT               ( GTX_0_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT0_RXUSRCLK_IN                 ( GTX_0_RXUSRCLK ),
    .GT0_RXUSRCLK2_IN                ( GTX_0_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT0_RXDATA_OUT                  ( GTX_0_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT0_GTXRXP_IN                   ( GTX_0_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT0_GTXRXN_IN                   ( GTX_0_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT0_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
//  .GT0_RXDFEAGCHOLD_IN             ( GTX_0_RXDFEAGCHOLD ),
    .GT0_RXLPMHFHOLD_IN              ( 1'b0 ),
    .GT0_RXLPMLFHOLD_IN              ( 1'b0 ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT0_RXOUTCLK_OUT                ( GTX_0_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT0_GTRXRESET_IN                ( GTX_0_GTRXRESET ),
    .GT0_RXPCSRESET_IN               ( GTX_0_RXPCSRESET ),
    .GT0_RXPMARESET_IN               ( GTX_0_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT0_RXRESETDONE_OUT             ( GTX_0_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT0_GTTXRESET_IN                ( GTX_0_GTTXRESET ),
    .GT0_TXUSERRDY_IN                ( GTX_0_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT0_TXUSRCLK_IN                 ( GTX_0_TXUSRCLK ),
    .GT0_TXUSRCLK2_IN                ( GTX_0_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT0_TXBUFSTATUS_OUT             ( GTX_0_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT0_TXDATA_IN                   ( GTX_0_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT0_GTXTXN_OUT                  ( GTX_0_GTXTXN ),
    .GT0_GTXTXP_OUT                  ( GTX_0_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT0_TXOUTCLK_OUT                ( GTX_0_TXOUTCLK ),
    .GT0_TXOUTCLKFABRIC_OUT          (  ),
    .GT0_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT0_TXPCSRESET_IN               ( GTX_0_TXPCSRESET ),
    .GT0_TXRESETDONE_OUT             ( GTX_0_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT1  (X0Y1)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT1_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT1_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT1_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT1_DRPDO_OUT                   (  ),
    .GT1_DRPEN_IN                    ( GTX_DRPEN ),
    .GT1_DRPRDY_OUT                  (  ),
    .GT1_DRPWE_IN                    ( GTX_DRPWE ),

    //----------------------------- Loopback Ports -----------------------------
    .GT1_LOOPBACK_IN                 ( GTX_1_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT1_RXUSERRDY_IN                ( GTX_1_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT1_EYESCANDATAERROR_OUT        ( GTX_1_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT1_RXCDRLOCK_OUT               ( GTX_1_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT1_RXUSRCLK_IN                 ( GTX_1_RXUSRCLK ),
    .GT1_RXUSRCLK2_IN                ( GTX_1_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT1_RXDATA_OUT                  ( GTX_1_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT1_GTXRXP_IN                   ( GTX_1_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT1_GTXRXN_IN                   ( GTX_1_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT1_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
//  .GT1_RXDFEAGCHOLD_IN             ( GTX_1_RXDFEAGCHOLD ),
    .GT1_RXLPMHFHOLD_IN              ( 1'b0 ),
    .GT1_RXLPMLFHOLD_IN              ( 1'b0 ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT1_RXOUTCLK_OUT                ( GTX_1_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT1_GTRXRESET_IN                ( GTX_1_GTRXRESET ),
    .GT1_RXPCSRESET_IN               ( GTX_1_RXPCSRESET ),
    .GT1_RXPMARESET_IN               ( GTX_1_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT1_RXRESETDONE_OUT             ( GTX_1_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT1_GTTXRESET_IN                ( GTX_1_GTTXRESET ),
    .GT1_TXUSERRDY_IN                ( GTX_1_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT1_TXUSRCLK_IN                 ( GTX_1_TXUSRCLK ),
    .GT1_TXUSRCLK2_IN                ( GTX_1_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT1_TXBUFSTATUS_OUT             ( GTX_1_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT1_TXDATA_IN                   ( GTX_1_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT1_GTXTXN_OUT                  ( GTX_1_GTXTXN ),
    .GT1_GTXTXP_OUT                  ( GTX_1_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT1_TXOUTCLK_OUT                ( GTX_1_TXOUTCLK ),
    .GT1_TXOUTCLKFABRIC_OUT          (  ),
    .GT1_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT1_TXPCSRESET_IN               ( GTX_1_TXPCSRESET ),
    .GT1_TXRESETDONE_OUT             ( GTX_1_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT2  (X0Y2)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT2_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT2_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT2_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT2_DRPDO_OUT                   (  ),
    .GT2_DRPEN_IN                    ( GTX_DRPEN ),
    .GT2_DRPRDY_OUT                  (  ),
    .GT2_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT2_LOOPBACK_IN                 ( GTX_2_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT2_RXUSERRDY_IN                ( GTX_2_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT2_EYESCANDATAERROR_OUT        ( GTX_2_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT2_RXCDRLOCK_OUT               ( GTX_2_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT2_RXUSRCLK_IN                 ( GTX_2_RXUSRCLK ),
    .GT2_RXUSRCLK2_IN                ( GTX_2_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT2_RXDATA_OUT                  ( GTX_2_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT2_GTXRXP_IN                   ( GTX_2_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT2_GTXRXN_IN                   ( GTX_2_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT2_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
//  .GT2_RXDFEAGCHOLD_IN             ( GTX_2_RXDFEAGCHOLD ),
    .GT2_RXLPMHFHOLD_IN              ( 1'b0 ),
    .GT2_RXLPMLFHOLD_IN              ( 1'b0 ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT2_RXOUTCLK_OUT                ( GTX_2_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT2_GTRXRESET_IN                ( GTX_2_GTRXRESET ),
    .GT2_RXPCSRESET_IN               ( GTX_2_RXPCSRESET ),
    .GT2_RXPMARESET_IN               ( GTX_2_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT2_RXRESETDONE_OUT             ( GTX_2_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT2_GTTXRESET_IN                ( GTX_2_GTTXRESET ),
    .GT2_TXUSERRDY_IN                ( GTX_2_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT2_TXUSRCLK_IN                 ( GTX_2_TXUSRCLK ),
    .GT2_TXUSRCLK2_IN                ( GTX_2_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT2_TXBUFSTATUS_OUT             ( GTX_2_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT2_TXDATA_IN                   ( GTX_2_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT2_GTXTXN_OUT                  ( GTX_2_GTXTXN ),
    .GT2_GTXTXP_OUT                  ( GTX_2_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT2_TXOUTCLK_OUT                ( GTX_2_TXOUTCLK ),
    .GT2_TXOUTCLKFABRIC_OUT          (  ),
    .GT2_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT2_TXPCSRESET_IN               ( GTX_2_TXPCSRESET ),
    .GT2_TXRESETDONE_OUT             ( GTX_2_TXRESETDONE ),

    //_________________________________________________________________________
    //_________________________________________________________________________
    //GT3  (X0Y3)
    //____________________________CHANNEL PORTS________________________________
    //-------------------------- Channel - DRP Ports  --------------------------
    .GT3_DRPADDR_IN                  ( GTX_DRPADDR[8:0] ),
    .GT3_DRPCLK_IN                   ( GTX_DRPCLK ),
    .GT3_DRPDI_IN                    ( GTX_DRPDI[15:0] ),
    .GT3_DRPDO_OUT                   (  ),
    .GT3_DRPEN_IN                    ( GTX_DRPEN ),
    .GT3_DRPRDY_OUT                  (  ),
    .GT3_DRPWE_IN                    ( GTX_DRPWE ),
    //----------------------------- Loopback Ports -----------------------------
    .GT3_LOOPBACK_IN                 ( GTX_3_LOOPBACK[2:0] ),
    //------------------- RX Initialization and Reset Ports --------------------
    .GT3_RXUSERRDY_IN                ( GTX_3_RXUSERRDY ),
    //------------------------ RX Margin Analysis Ports ------------------------
    .GT3_EYESCANDATAERROR_OUT        ( GTX_3_EYESCANDATAERROR ),
    //----------------------- Receive Ports - CDR Ports ------------------------
    .GT3_RXCDRLOCK_OUT               ( GTX_3_RXCDRLOCK ),
    //---------------- Receive Ports - FPGA RX Interface Ports -----------------
    .GT3_RXUSRCLK_IN                 ( GTX_3_RXUSRCLK ),
    .GT3_RXUSRCLK2_IN                ( GTX_3_RXUSRCLK2 ),
    //---------------- Receive Ports - FPGA RX interface Ports -----------------
    .GT3_RXDATA_OUT                  ( GTX_3_RXDATA[15:0] ),
    //------------------------- Receive Ports - RX AFE -------------------------
    .GT3_GTXRXP_IN                   ( GTX_3_GTXRXP ),
    //---------------------- Receive Ports - RX AFE Ports ----------------------
    .GT3_GTXRXN_IN                   ( GTX_3_GTXRXN ),
    //----------------- Receive Ports - RX Buffer Bypass Ports -----------------
    .GT3_RXBUFSTATUS_OUT             (  ),
    //------------------- Receive Ports - RX Equalizer Ports -------------------
//  .GT3_RXDFEAGCHOLD_IN             ( GTX_3_RXDFEAGCHOLD ),
    .GT3_RXLPMHFHOLD_IN              ( 1'b0 ),
    .GT3_RXLPMLFHOLD_IN              ( 1'b0 ),
    //------------- Receive Ports - RX Fabric Output Control Ports -------------
    .GT3_RXOUTCLK_OUT                ( GTX_3_RXOUTCLK ),
    //----------- Receive Ports - RX Initialization and Reset Ports ------------
    .GT3_GTRXRESET_IN                ( GTX_3_GTRXRESET ),
    .GT3_RXPCSRESET_IN               ( GTX_3_RXPCSRESET ),
    .GT3_RXPMARESET_IN               ( GTX_3_RXPMARESET ),
    //------------ Receive Ports -RX Initialization and Reset Ports ------------
    .GT3_RXRESETDONE_OUT             ( GTX_3_RXRESETDONE ),
    //------------------- TX Initialization and Reset Ports --------------------
    .GT3_GTTXRESET_IN                ( GTX_3_GTTXRESET ),
    .GT3_TXUSERRDY_IN                ( GTX_3_TXUSERRDY ),
    //---------------- Transmit Ports - FPGA TX Interface Ports ----------------
    .GT3_TXUSRCLK_IN                 ( GTX_3_TXUSRCLK ),
    .GT3_TXUSRCLK2_IN                ( GTX_3_TXUSRCLK2 ),
    //-------------------- Transmit Ports - TX Buffer Ports --------------------
    .GT3_TXBUFSTATUS_OUT             ( GTX_3_TXBUFSTATUS[1:0] ),
    //---------------- Transmit Ports - TX Data Path interface -----------------
    .GT3_TXDATA_IN                   ( GTX_3_TXDATA[15:0] ),
    //-------------- Transmit Ports - TX Driver and OOB signaling --------------
    .GT3_GTXTXN_OUT                  ( GTX_3_GTXTXN ),
    .GT3_GTXTXP_OUT                  ( GTX_3_GTXTXP ),
    //--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
    .GT3_TXOUTCLK_OUT                ( GTX_3_TXOUTCLK ),
    .GT3_TXOUTCLKFABRIC_OUT          (  ),
    .GT3_TXOUTCLKPCS_OUT             (  ),
    //----------- Transmit Ports - TX Initialization and Reset Ports -----------
    .GT3_TXPCSRESET_IN               ( GTX_3_TXPCSRESET ),
    .GT3_TXRESETDONE_OUT             ( GTX_3_TXRESETDONE ),


    //____________________________COMMON PORTS________________________________
    //-------------------- Common Block  - Ref Clock Ports ---------------------
    .GT0_GTREFCLK0_COMMON_IN         ( GTX_REFCLK ),
    //----------------------- Common Block - QPLL Ports ------------------------
    .GT0_QPLLLOCK_OUT                ( GTX_QPLLLOCK ),
    .GT0_QPLLLOCKDETCLK_IN           ( GTX_QPLLLOCKDETCLK ),
    .GT0_QPLLREFCLKLOST_OUT          ( GTX_QPLLREFCLKLOST ),
    .GT0_QPLLRESET_IN                ( GTX_QPLLRESET )
    );


endmodule

